1. Field of the Invention
The present invention relates to a method for the making of the metallizations of a transistor, the insulation of which is obtained by the making, on the vertical walls, of a pattern used to self-align these metallizations. This method can be applied to the vertical components using a metallization manufactured by the self-alignment technique. It enables eliminating the risks of short-circuits on the flanks of the vertical pattern.
2. Description of the Prior Art
The term "vertical components" is generally applied to those in which the current is conveyed perpendicularly to the surface of the substrate. These components comprise a stack of layers of semiconductor materials, at least one layer of which is etched in the form of a mesa, i.e. it forms a raised pattern that generally bears an electrode metallization. Thus, heterojunction bipolar transistors (or HPTs) are vertical components: the emitter, the base and the collector are on three different levels. There are certain transistors, for example SISFETs (semiconductor-insulation-semiconductor FETs), in which the current flows parallel to the surface of the substrate but which nonetheless can be considered to be vertical components from the viewpoint of the invention, inasmuch as they have an etched mesa pattern used to self-align two types of metallizations.
These vertical components have so-called "double mesa" structures for which the technology dictates at least two etchings used to uncover the base and demarcate the collectors, if the transistor referred to is a bipolar transistor, or else the gate and the source/drain if the transistor referred to is a field-effect transistor. To simplify the explanation of the invention, it shall be presented with reference to the example of a bipolar transistor.
One of the limitations of this type of component arises out of the access resistances of the base as well as the base-collector capacitances in the case of an HBT. The most efficient approach to reducing these parasitic phenomena lies in carrying out the self-alignment of the base with respect to the emitter.
The difficulty of self-alignment methods arises out of the risks of the short-circuiting of the emitter-base metal contacts. For, it is commonly the mesa of the emitter that will act as a self-alignment mask for the base metallization: when the metal is evaporated, there is a real risk that traces of metal on the flanks of the mesa might lead to an emitter-base short-circuit. Various techniques are commonly used to prevent these short circuits. These are:
either a side-wall type deposition of an insulator on the flanks of the emitter, followed by an anisotropic evaporation of the base metallization. The metal traces on the flanks of the mesa are then eliminated by ion bombardment. The method is a delicate one by its very essence, and depends a great deal on the evaporation systems used.
or the etching of the semiconductor layer of the emitter in a T shape. This enables the creation of a helmet that creates a shadow phenomenon during the evaporation of the base metal and thus prevents the problems of short-circuits. The limitations of this technique arise out of the uncertainties of etching of the foot of the emitter. The geometry of the emitter is not controlled with precision,
or again the metallization of the emitter is mushroom-shaped. The semiconductor material is then chemically etched from the foot of the metallization onwards. A helmet enabling self-alignment is thus created. The major drawback of this technique arises out of the fact of resorting to chemical etching processes which sometimes raise problems and lack precision and reliability.